The present invention relates to a discharge control circuit for a battery, and more particularly, to a discharge control circuit that prevents an over-discharge of a battery incorporated in a portable electric device.
In recent years, many portable electronic devices have employed lithium ion batteries, and extending the life of such battery will require securely preventing an over-discharge of the battery.
FIG. 1 is a schematic diagram of a conventional discharge control circuit 100. A battery 1 that provides a power supply for a portable electric device includes a lithium ion battery in which three cells 2a, 2b, 2c are connected in series.
The discharge control circuit 100 controls a discharge current flowing in a portable electric device from the battery 1. The control circuit 100 includes a control circuit 3, a discharge control switch 4 connected to the control circuit 3, and a capacitor 5 connected to the control circuit 3. The switch 4 and the capacitor 5 are externally mounted.
The discharge control switch 4 is a P-channel MOS transistor. The positive terminal of the battery 1 is connected to an output terminal t1 via the discharge control switch 4, and the negative terminal thereof is connected to the GND terminal and an output terminal t2.
When the discharge control switch 4 is turned on, a power supply voltage and a discharge current are supplied to the portable electric device from the output terminals t1, t2. When the portable electric device is started to operate, a supply voltage Vcc, which depends on a power supply circuit of the portable electric device, is supplied between the output terminals t1, t2.
The discharge control switch 4 is controlled by a control signal Dout from the control circuit 3. The negative terminals of comparators 6a, 6b, 6c of the control circuit 3 are connected to the positive terminals of the cells 2a, 2b, 2c. The positive terminals of the comparators 6a, 6b, 6c are supplied with a reference voltage Vth that is higher by a specific amount than the voltages at the negative terminals of the cells 2a, 2b, 2c. 
The reference voltage Vth is set at, for example, 2.8 V in relation to the cell voltage Vce of 4.2 V when the cells 2a, 2b, 2c are fully charged.
When the cell voltages Vce of the cells 2a-2c exceed 2.8 V, the comparators 6a-6c generate L-level comparator output signals. When the cell voltages Vce of the cells 2a-2c are equal to or lower than 2.8 V, the comparators 6a-6c generate H-level comparator output signals.
The comparator output signals are supplied to a NOR gate 7a, and the output signal of the NOR gate 7a is supplied to the first input terminal of an OR gate 8a and to the first input terminal of an AND gate 9a. When all of the comparator output signals are at L-level, the output signal of the NOR gate 7a goes high. The comparators 6a-6c and the NOR gate 7a form a cell voltage detector 15.
The output signal of the OR gate 8a is supplied to the gate of an N-channel MOS transistor Tr1. The drain (node N1) of the NMOS transistor Tr1 is connected to the first terminal of the capacitor 5 and to a current source 10 that supplies a current I1. The second terminal of the capacitor 5 is connected to the GND.
When the transistor Tr1 is turned on by the OR gate 8a with H-level output signal, the current I1 supplied by the current source 10 flows through the transistor Tr1 as a drain current. When the transistor Tr1 is turned off, the current I1 charges the capacitor 5, and the voltage of the node N1 increases accordingly.
The node N1 is connected to the set terminal S of a latch circuit 11. When the voltage of the node N1 is at the H-level, the output terminal Q of the latch circuit 11 delivers the latch output signal Dout at the H-level.
The reset terminal R of the latch circuit 11 is supplied with the output signal from the AND gate 9a. When output signal of the AND gate 9a is at the H-level, the latch output signal Dout goes low. When an H-level signal is supplied to the set terminal S and to the reset terminal R, the latch circuit 11 outputs the L-level latch output signal Dout.
The latch output signal Dout is supplied to the second input terminal of the OR gate 8a, an inverter circuit 12a, and the gate of the discharge control switch 4. When the latch output signal Dout is at the L-level, the discharge control switch 4 is turned on, and an output voltage Voc, which is substantially equal to the battery supply voltage Vcc, and a discharge current are supplied to the load circuit from the output terminal t1.
The output signal of the inverter circuit 12a is supplied to the first input terminal of a NOR gate 7b, and the output voltage Voc of the output terminal t1 is supplied to the second input terminal of the NOR gate 7b. The output signal of the NOR gate 7b is supplied to the gate of a P-channel MOS transistor Tr2. The source of the transistor Tr2 is supplied with the supply voltage Vcc from the battery 1, and the drain of the transistor Tr2 is connected to a bias generating circuit 13.
When the voltage Voc at the output terminal t1 becomes higher than the threshold Nth of the NOR gate 7b, or when the latch output signal Dout and output signal of the NOR gate 7b are at the L-level, the transistor Tr2 is turned on to supply the bias generating circuit 13 with the supply voltage Vcc.
When supplied with the supply voltage Vcc, the bias generating circuit 13 supplies bias voltages to the current source 10 and the comparators 6a-6c. 
The second input terminal of the AND gate 9a is supplied with the output voltage Voc. The AND gate 9a has the same threshold as the NOR gate 7b. The OR gate 8a, the transistor Tr1, the current source 10, the capacitor 5, and the AND gate 9a form a delay time setting circuit 14.
In the discharge control circuit 100, when each of the cell voltages Vce of the cells 2a-2c of the battery 1 is higher than the reference voltage Vth, all of output signals of the comparator are at the L-level, and output signal of the NOR gate 7a is at the H-level. Accordingly, the output signal of the OR gate 8a is at the H-level, the transistor Tr1 is turned on, and the current I1 supplied from the current source 10 flows through the transistor Tr1 as a drain current. As the result, the voltage of the node N1 and the latch output signal Dout are at the L-level. The latch output signal Dout at the L-level turns the discharge control switch 4 on, which supplies the load circuit with the power supply voltage Vcc from the battery 1 via the output terminal t1. At this time, since the voltage Voc at the output terminal t1 is at the H-level, both the input terminals of the AND gate 9a are supplied with the H-level signals, and the H-level AND gate 9a output signal is supplied to the reset terminal R of the latch circuit 11, which holds the latch output signal Dout at the L-level.
Since the NOR gate 7b is supplied with the H-level voltage Voc and the H-level inverter circuit 12a output signal, the output signal of the NOR gate 7b is at the L-level, the transistor Tr2 is turned on, and the bias generating circuit 13 is supplied with the supply voltage Vcc.
As shown in FIG. 2, when at least one of the cell voltages Vce of the cells 2a-2c becomes lower than the reference voltage Vth, at least one of the comparator output signals is at the H-level. Since the output signal of the NOR gate 7a is at the L-level accordingly, the input terminals of the OR gate 8a are supplied with the L-level signals, and the transistor Tr1 is turned off. Thus, the current source 10 supplies the current I1 to charge the capacitor 5, therefore increasing the voltage of the node N1 gradually.
When the voltage of the node N1 reaches the threshold Lth of the set terminal S of the latch circuit 11 at a delay time Td after the transistor Tr1 is turned off, the latch output signal Dout is at the H-level, and the discharge control switch 4 is turned off. In consequence, the output voltage Voc decreases. When the output voltage Voc is lower than the threshold Nth of the NOR gate 7b, the NOR gate 7b output signal is at the H-level, and the transistor Tr2 is turned off, which disconnects the supply of the power supply Vcc to the bias generating circuit 13.
The H-level output signal Dout brings the output signal of the OR gate 8a into an H-level to turn the transistor Tr1 on again, and the potential at the node N1 decreases to the GND level. This operation completely cuts off the current supply from the battery 1 to the load circuit and to the circuits in the discharge control circuit, which prevents an over discharge of the battery 1.
When the cell voltages Vce of the cells 2a-2c exceed the reference voltage Vth of the comparators 6a-6c, the transistor Tr1 is turned on, and the voltage of the node N1 is at the L-level. At this time, since the output signal of the AND gate 9a is at the H-level, the latch output signal Dout is at the L-level, the discharge control switch 4 is turned on, the output voltage Voc, which is substantially equal to the power supply voltage Vcc, and the discharge current are supplied to the load circuit from the battery 1 via the discharge control switch 4.
However, in case that the load circuit connected between the output terminals t1, t2 includes a capacitance, it takes a predetermined time for the output voltage Voc goes lower than the threshold Nth of the NOR gate 7b after the discharge control switch 4 is turned off, and the bias generating circuit 13 is continuously supplied with the power supply voltage Vcc during this time. This case has the drawbacks as follows.
As shown in FIG. 3, when the discharge control switch 4 is turned off to cut off the discharge currents of the cells 2a-2c, there is a possibility that the cell voltage Vce of the cells 2a-2c instantaneously rises to exceed the reference voltage Vth. After the discharge control switch 4 is turned off, before the output voltage Voc goes lower than the threshold Nth of the NOR gate 7b and the AND gate 9a, if the cell voltage Vce exceeds the reference voltage Vth, all of output signals of the comparator are at the L-level, output signal of the NOR gate 7a is at the H-level, and output signal of the AND gate 9a is at the H-level, so that the latch output signal Dout returns to L-level, which turns the discharge control switch 4 on, and therefore starts the discharge operation again. When the cell voltage Vce goes lower than the reference voltage Vth, the discharge control switch 4 is turned off again, after the delay time Td. This operation is repeated until it disappears that the cell voltage Vce rises higher than the reference voltage Vth immediately after the stop of discharge. Therefore, the conventional technique, involving this operation, cannot securely prevent the over-discharge of the battery 1.
An object of the present invention is to provide a discharge control circuit that securely prevents an over-discharge of a battery.
In one aspect of the present invention a discharge control circuit is provided that controls discharge of a battery including at least one cell. The control circuit includes a discharge control switch, which is connected to the battery, that cuts off a discharge current of the battery in response to a discharge stop signal. A control circuit is connected to the battery and the discharge control switch to generate the discharge stop signal for deactivating the discharge control switch when at least one cell voltage reaches a lower limit. The control circuit includes a switch holding circuit for continuously supplying the discharge stop signal to the discharge control switch for a predetermined time after the discharge stop signal is generated regardless of the cell voltage.
In another aspect of the present invention, a discharge control circuit is provided for controlling discharge of a battery including at least one cell. The control circuit includes a discharge control switch, which is connected to the battery, that cuts off a discharge current of the battery in response to a discharge stop signal. A cell voltage detecting circuit is connected to the battery to generate a cell voltage detection signal when at least one cell voltage reaches a lower limit. A delay time setting circuit is connected to the cell voltage detecting circuit to generate the discharge stop signal after a first predetermined time from the moment that the cell voltage detection signal is generated. A latch circuit is connected to the delay time setting circuit to latch the discharge stop signal and supply the discharge control switch with the latched discharge stop signal. The delay time setting circuit includes a switch holding circuit for invalidating the cell voltage detection signal in a second predetermined time after the latched discharge stop signal is supplied and continuously supplying the latched discharge stop signal in this time.
In another aspect of the present invention, a discharge control circuit is provided for controlling discharge of a battery including at least one cell. The control circuit includes a discharge control switch connected to the battery, for cutting off a discharge current of the battery in response to a discharge stop signal. A cell voltage detecting circuit is connected to the battery to generate a cell voltage detection signal when at least one cell voltage reaches a lower limit. A delay time setting circuit is connected to the cell voltage detecting circuit to generate the discharge stop signal after a first predetermined time from the moment that the cell voltage detection signal is generated. A first latch circuit is connected to the delay time setting circuit to latch the discharge stop signal and supplies the discharge control switch with the latched discharge stop signal. A second latch circuit is connected to the first latch circuit to perform a set operation in response to the latched discharge control signal and invalidate a reset operation of the first latch circuit for a second predetermined time after the latched discharge stop signal is supplied.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.